Recently, a system using small-amplitude differential signals (low voltage differential signaling: LVDS) is adopted in signal transmission between a graphic board and a display unit of a personal computer and the like. According to this system, EMI (electromagnetic interference) can be suppressed compared to the case where a digital signal is transmitted in full swing.
In FIG. 1, an example of a conventional line driver used in the LVDS system is shown. This line driver includes N-channel MOS transistors QN11 to QN14 for performing switching operation as differential signals In1 and In2 are input to the gates thereof, a constant current source CS for supplying constant current from a power supply potential VDD on the higher voltage side to the transistors QN11 and QN13, an N-channel MOS transistor QN15 connected between a source (node 102) of the transistors QN12 and QN14 and a power supply potential VSS on the lower voltage side, and an operational amplifier OP11 for controlling a gate voltage of the transistor QN15.
To a non-inverting input of the operational amplifier OP11, a reference potential VREF is supplied, and, to an inverting input of the operational amplifier OP11, a potential of the node 102 is fed back. Thereby, the potential of the node 102 is controlled so as to approach the reference potential VREF.
The potentials of the respective input signals In1 and In2 vary in a range from the power supply potential VSS on the lower voltage side to the power supply potential VDD on the higher voltage side. In accordance with this, the transistors QN11 to QN14 perform switching operation. For example, when the input signal In1 is at a low level and the input signal In2 is at a high level, the transistors QN11 and QN14 assume an off-state and the transistors QN12 and QN13 assume an on-state. Thereby, current ID flows in a terminating resistance RT on the reception side and an output voltage ΔV=ID×RT is generated between a node 100 and a node 101.
Further, assuming that the potentials of the node 100 and the node 101 are V100 and V101, respectively, an offset potential VOS of the differential outputs is expressed by VOS=(V100+V101)/2. The reference potential VREF supplied to the non-inverting input of the operational amplifier OP11 is determined so that the offset potential VOS takes a target value.
However, in the line driver shown in FIG. 1, when the transistors QN11 to QN14 are switched frequently, the potential variation of the node 102 becomes greater and the offset potential VOS is apt to become unstable. In order to improve this, it is conceivable that the open gain of the operational amplifier OP11 is increased, however, on the other hand, a problem arises that the operational amplifier OP11 becomes apt to oscillate due to power supply noise etc. Further, it is necessary to vary both the constant current source CS and the reference potential VREF in order to change the output voltage ΔV with the offset potential VOS kept constant, and accordingly, the circuit for generating these becomes complicated.
In FIG. 2, another example of the conventional line driver used in the LVDS system is shown. This line driver includes N-channel MOS transistors QN21 to QN24 for performing switching operation as differential signals In1 and In2 are input to the gates thereof, an N-channel MOS transistor QN26 connected between a power supply potential VDD on the higher voltage side and a drain (node 203) of the transistors QN21 and QN23, an operational amplifier OP21 for controlling a gate voltage of the transistor QN26, an N-channel MOS transistor QN25 connected between a source (node 202) of the transistors QN22 and QN24 and a power supply potential VSS on the lower voltage side, and an operational amplifier OP22 for controlling a gate voltage of the transistor QN25.
To a non-inverting input of the operational amplifier OP21, a reference potential VREF1 is supplied, and, to an inverting input of the operational amplifier OP21, a potential of the node 203 is fed back. Thereby, the potential of the node 203 is controlled so as to approach the reference potential VREF1. Similarly, to a non-inverting input of the operational amplifier OP22, a reference potential VREF2 is supplied, and, to an inverting input of the operational amplifier OP22, a potential of the node 202 is fed back. Thereby, the potential of the node 202 is controlled so as to approach the reference potential VREF2.
The potentials of the respective input signals In1 and In2 vary in a range from the power supply potential VSS on the lower voltage side to the power supply potential VDD on the higher voltage side. In accordance with this, the transistors QN21 to QN24 perform switching operation. For example, when the input signal In1 is at the low level and the input signal In2 is at the high level, the transistors QN21 and QN24 assume the off-state and the transistors QN22 and QN23 assume the on-state. Thereby, the node 200 has a high output potential VOH and the node 201 has a low output potential VOL, and an output voltage ΔV=VOH−VOL is generated between the node 200 and the node 201.
Here, the reference potential VREF1 and the reference potential VREF2 respectively supplied to the non-inverting inputs of the operational amplifiers OP21 and OP22 are determined so that the output potentials VOH and VOL take target values. An offset potential VOS of the differential outputs is expressed by VOS=(VOH+VOL)/2.
However, in the line driver shown in FIG. 2, when the transistors QN21 to QN24 are switched frequently, the potential variation of the nodes 203 and 202 also become greater and the output potentials VOH and VOL are apt to become unstable. Therefore, the line driver shown in FIG. 2 also has the same problem as that of the line driver shown in FIG. 1. Further, it is necessary to vary both the reference potential VREF1 and the reference potential VREF2 in order to change the output voltage ΔV with the offset potential VOS kept constant, and accordingly, the circuit for generating these becomes complicated.
On the other hand, in U.S. Pat. No. 6,111,431, a line driver of LVDS system as shown in FIG. 3 is disclosed. This line driver is constituted by a driver circuit 32 and a replica circuit 31 (referred to as “mimicking circuit”) for controlling the operation of the driver circuit 32.
The driver circuit 32 includes N-channel MOS transistors QN31 to QN34 for performing switching operation as differential signals In1 and In2 are input to the gates thereof, a P-channel MOS transistor QP31 connected between a power supply potential VDD on the higher voltage side and a drain (node 303) of the transistors QN31 and QN33, an operational amplifier OP31 for controlling a gate voltage of the transistor QP31, an N-channel MOS transistor QN35 connected between a source (node 302) of the transistors QN32 and QN34 and a power supply potential VSS on the lower voltage side, and an operational amplifier OP32 for controlling a gate voltage of the transistor QN35.
In order to supply predetermined potentials to a non-inverting input (node 304) of the operational amplifier OP31 and a non-inverting input (node 305) of the operational amplifier OP32, the replica circuit 31 is connected thereto. The replica circuit 31 includes a P-channel MOS transistor QP32 and N-channel MOS transistors QN36 to QN38 having 1/n sizes of the transistors QP31 and QN31 to QN35 used in the driver circuit 32, respectively, and two resistances each having resistance values of n/2 times that of the terminating resistance RT on the reception side.
The transistor QP32 is connected between the power supply potential VDD on the higher voltage side and a drain (node 304) of the transistor QN36. In the transistor QP32, there flows a drain current of 1/n of the drain current ID flowing in the transistor QP31 of the driver circuit 32. The transistors QN36 and QN37 constantly assume the on-state. The transistor QN38 is connected between a source (node 305) of the transistor QN37 and the power supply potential VSS on the lower voltage side.
Furthermore, the replica circuit 31 includes a current mirror circuit CMC for determining the drain current of the transistor QP32 and an operational amplifier OP33 for controlling a gate voltage of the transistor QN38.
To a non-inverting input of the operational amplifier OP33, a reference potential VREF is supplied, and, to an inverting input of the operational amplifier OP33, a potential of the node 306 is fed back. Thereby, the potential of the node 306 is controlled so as to approach the reference potential VREF.
The potentials of the respective input signals In1 and In2 vary in a range from the power supply potential VSS on the lower voltage side to the power supply potential VDD on the higher voltage side. In accordance with this, the transistors QN31 to QN34 perform switching operation. For example, when the input signal In1 is at the low level and the input signal In2 is at the high level, the transistors QN31 and QN34 assume the off-state and the transistors QN32 and QN33 assume the on-state. Thereby, current ID flows in the terminating resistance RT on the reception side and an output voltage ΔV=ID×RT is generated between the node 300 and the node 301. The current flowing in the transistor QP32 of the replica circuit 31 is determined so that the output voltage ΔV may take a target value.
Further, assuming that the potentials of the node 300 and the node 301 are V300 and V301, respectively, an offset potential of the differential output is expressed by VOS=(V300+V301)/2. The offset potential VOS varies in conjunction with the potential of the connection point (node 306) between the two resistances in the replica circuit 31. Therefore, the reference potential VREF supplied to the non-inverting input of the operational amplifier OP33 is determined so that the offset potential VOS, i.e. the potential of the node 306 takes a target value.
The line driver shown in FIG. 3 is a circuit suitable for changing the output voltage ΔV with the offset potential VOS kept constant. However, the use of the three operational amplifiers makes the circuit complicated. Further, there is a problem that the operational amplifiers OP31 and OP32 for controlling the transistors QP31 and QN35 in which great current flows are apt to oscillate with the power noise etc. as a trigger.